1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a semiconductor integrated circuit system, and more specifically, it relates to a structure for reducing power consumption.
2. Description of the Prior Art
A data hold mode in a conventional asynchronous SRAM (SRAM: Static Random Access Memory) is described with reference to FIG. 35. In order to set the SRAM in the data hold mode, a chip selection signal /CS is set in a nonselective state (high) for taking a setup period tsu(PD) and a power supply voltage Vdd is stepped down to a data hold mode voltage. The SRAM is set in the data hold mode having low power consumption due to the step-down of the voltage applied thereto.
In order to return the SRAM from the data hold mode to an operating mode, the power supply voltage Vdd is returned to an operating voltage and the chip selection signal /CS is returned to a selective state (set low) through a recovery time trec(PD).
FIGS. 36A and 36B illustrate exemplary input circuits 200 and 201 included in the asynchronous SRAM. The input circuit 200 includes PMOS transistors P50 and P51 and NMOS transistors N50 and N51. The transistors P50, N50 and N51 are connected between a power supply node Vdd receiving the operating voltage and ground power. The gates of the transistors P50 and N50 receive an input signal to be captured. A signal from a node Z50 between the transistors P50 and N50 is transferred to an internal circuit. The gate of the transistor N51 receives an internal chip selection signal (internal CS signal) corresponding to a chip selection signal /CS. The transistor P51 is connected between the node Z50 and a power supply node Vdd, and receives the internal CS signal in the gate thereof.
The input circuit 201 includes PMOS transistors P52 and P53 and NMOS transistors N52 and N53. The transistors P52, P53 and N53 are connected between a power supply node Vdd and ground power. The gates of the transistors P53 and N53 receive an input signal to be captured. A signal from a node Z51 between the transistors P53 and N53 is transferred to an internal circuit. The gate of the transistor P52 receives a signal (internal /CS signal) obtained by inverting an internal chip selection signal. The transistor N52 is connected between the node Z51 and the ground power, and receives the internal /CS signal in the gate thereof. When a chip selection signal is nonselective, the input initial stage is inactivated so that no current flows regardless of the input signal.
A synchronous SRAM has a snooze mode, in order to suppress power consumption. The snooze mode is now described with reference to FIG. 37. FIG. 37 shows a clock signal CLK, a snooze mode signal ZZ, an address status controller signal /ADSC, a write enable signal /WE and an output enable signal /OE as input signals.
In order to set the SRAM in the snooze mode, the control signals excluding the snooze mode signal ZZ are inactivated and thereafter the snooze mode signal ZZ is activated (high). The SRAM enters a snooze state after a lapse of a setup time.
In the snooze state, fluctuation of the signals excluding the output enable signal /OE exerts no influence on the SRAM. In the smooth mode, the SRAM has low power consumption regardless of external signals.
In order to return the SRAM from the snooze mode to an operating mode, the snooze mode signal ZZ is set low. The synchronous SRAM becomes operable after a lapse of a recovery time.
FIGS. 38A and 38B illustrate exemplary input circuits 202 and 203 having a snooze mode function included in the synchronous SRAM. The input circuit 202 includes PMOS transistors P54 and P55 and NMOS transistors N54 and N55. The transistors P54, N54 and N55 are connected between a power supply node Vdd and ground power. The gates of the transistors P54 and N54 receive an input signal to be captured. A signal from a node Z52 between the transistors P54 and N54 is transferred to an internal circuit. The gate of the transistor N55 receives an internal snooze mode signal (internal ZZ signal) corresponding to the snooze mode signal ZZ. The transistor P55 is connected between the node Z52 and a power supply node Vdd, and receives the internal ZZ signal in the gate thereof.
The input circuit 203 includes PMOS transistors P56 and P57 and NMOS transistors N56 and N57. The transistors P56, P57 and N57 are connected between a power supply node Vdd and ground power. The gates of the transistors P57 and N57 receive an input signal to be captured. A signal from a node Z53 between the transistors P57 and N57 is transferred to an internal circuit. The gate of the transistor P56 receives a signal (internal /ZZ signal) obtained by inverting an internal snooze mode signal. The transistor N56 is connected between the node Z53 and the ground power, and receives the internal /ZZ signal in its gate. In the snooze mode, the input initial stage is inactivated so that no current flows regardless of the input signal. The chip selection signal /CS and the snooze mode signal ZZ may be ANDed when generating the internal ZZ signal.
A power down mode of a synchronous DRAM (DRAM: Dynamic Random Access Memory) is now described with reference to FIG. 39. FIG. 39 shows a clock signal CLK and a clock enable signal CKE as input signals.
In the power down mode, the clock enable signal CKE is set low thereby inactivating an internal clock of the device and suppressing power consumption of the device.
Thus, both of synchronous and asynchronous memory chips have a function for enabling suppression of power consumption.
However, the conventional synchronous SRAM still consumes power of about several mW in the snooze mode, and reduction of power consumption is insufficient for applying the synchronous SRAM to a portable terminal or the like.
In the asynchronous SRAM, power consumption can be suppressed due to the data hold mode. In actual operation, however, the SRAM receives no signal for performing a synchronous operation and hence an ATD (address transition detect) circuit or a DTD (data transition detect) circuit must be provided in the SRAM for generating internal write and read control signals. Such a specific circuit increases the operating current as a result. Further, it is difficult to design a circuit finely controlling the internal timing.
In addition, a signal forming the basis of a read timing is internally generated. Therefore, a sense amplifier based on a current mirror type having a low possibility of false reading is employed so that data can be reliably read from a memory cell in consideration of timing deviation. In this case, however, current must be regularly fed to result in feeding of excess current.
In the synchronous SDRAM, power consumption must be reduced not only in the power down mode but also in an operating mode.